The present invention relates to a semiconductor integrated circuit device using a CMOS and, more particularly, to a technique for realizing a semiconductor integrated circuit device in which a logic circuit and a memory are formed on the same substrate without complicating a manufacturing process.
A conventional technique of increasing the operating speed of a logic circuit is disclosed in JP-Laid Open No. Hei10-65517. In the conventional technique, while improving the operating speed by using a transistor of a low threshold voltage in a signal path for determining the operating speed or what is called a critical path, a leakage current is reduced by using transistors of middle or high threshold voltages for the other signal paths.
The enhancement of performance of an integrated circuit device using a CMOS has been realized by enhancement of performance and increase in packing density of transistors by making the gate in each of NMOS and PMOS transistors finer and reducing the thickness of a gate oxide film. In association with the enhancement, the supply voltage has been also decreased so that the electric field intensity is not increased by the finer gate and thinner film. For example, in the generation of a gate length of 0.35 xcexcm as a typical example in industry, the supply voltage is 3.3V. On the other hand, in the generation of the gate length of 0.25 xcexcm, the supply voltage is 2.5V.
Since further decrease in the supply voltage in association with the finer gate in the future is expected, if the threshold voltage is not decreased as well, the operating speed of the integrated circuit largely deteriorates. When the threshold voltage is decreased, however, a subthreshold current increases and the leakage current increases. In the conventional technique, consequently, a method of setting three threshold voltages for a logic circuit and decreasing the threshold of a transistor in a circuit in especially a signal path which determines the operating speed is employed. In the conventional technique, however, since three threshold values are created, the manufacturing method is complicated.
On the other hand, the scale of an integrated circuit device in recent years is becoming greater. Not only a logic circuit but also circuits such as a considerably large-scaled memory, an input output interface, a PLL and a clock are mounted on a chip.
Such circuits have, however, different characteristics and the characteristics of transistors required according to the characteristics of the circuits vary. For example, the threshold of a memory cell of an SRAM comprising six transistors, which is used together with a logic circuit cannot be decreased to a certain voltage or lower in order to realize electric stability. When the threshold of a memory cell in a DRAM comprising a capacitor and a transistor is decreased, charges accumulated in the capacitor are discharged by a leakage of the transistor. Consequently, the threshold cannot be decreased to a certain voltage or lower. The input and output voltages are determined by a specification and are higher than the internal operating voltage. An input output interface circuit inserted between them is therefore required to have the channel length and a gate oxide film which can stand at a high withstand voltage.
The optimum gate length, gate oxide film and threshold voltage vary according to the characteristics of the circuits in the integrated circuit device. When a semiconductor integrated circuit device in which the circuits are integrated on the same substrate is manufactured in accordance with the characteristics of the respective circuits, the manufacturing process is complicated. It is therefore feared that the manufacturing cost increases in association with deterioration in yield and increase in the number of manufacturing days.
The present invention provides a semiconductor integrated circuit device means capable of manufacturing even a semiconductor integrated circuit device in which the supply voltage to the logic circuit is low and various kinds of circuits exist on the same substrate at low cost without complicating the manufacturing process.
In order to solve the problems, according to the invention, there is provided a semiconductor integrated circuit device comprising: a logic circuit; and a memory cell array on which memory cells are integrated, wherein the logic circuit has; a first logic gate including an NMOS transistor having a first threshold voltage and a PMOS transistor having a third threshold voltage; and a second logic gate including an NMOS transistor having a second threshold voltage and a PMOS transistor having a fourth threshold voltage,
the memory cell array is a memory cell array on which a static memory cell comprising two load MOS transistors, two drive MOS transistors, and two transfer MOS transistors is integrated,
the two load MOS transistors are PMOS transistors each having the fourth threshold voltage,
the two drive MOS transistors are NMOS transistors each having the second threshold voltage,
the first threshold voltage is smaller than the second threshold voltage, and
the absolute value of the third threshold voltage is smaller than the absolute value of the fourth threshold voltage. The logic circuit and the SRAM memory cell are designed so as to satisfy the conditions.
In the invention, the logic circuit uses transistors of high and low thresholds, a high threshold transistor is used as at least the drive MOS transistor in the SRAM memory cell and a high threshold transistor having a thicker gate oxide film with the same dose of impurities in a channel is used as the transfer MOS transistor in the DRAM memory cell, and the input output circuit uses a transistor having a thicker gate oxide film with either the impurity concentration at the time of the high threshold or the impurity concentration at the time of the low threshold. By the means, the transistors optimum for the respective circuits can be manufactured without increasing the number of processes.
The logic circuit in the specification denotes a circuit region in which a combination of logic gates is provided except for the memory cell array, and comprises a data path including a register file and an execution unit and a control logic. The high (low) threshold denotes a high (low) threshold of which absolute value is high in the PMOS transistor. Generally, the threshold of the PMOS transistor and that of the NMOS transistor are different from each other. The high and low thresholds denotes high and low thresholds in each type of the channels.